The S_AXI_ACLK input is only used when Debug
register access is enabled, and AXI4-Lite slave
interconnect is used, or when BSCAN is disabled. Then it should normally be set to the same
clock as the interconnect.
The M_AXI_ACLK input is used when System Bus
Memory Access or Embedded Trace Interface is enabled, and AXI4 master interconnect and/or LMB master interfaces are used. Then it must be
set to the same clock as the interconnect and LMB interfaces. Different clocks for AXI4 and LMB is not supported in this case.
Apart from Debug register access, the MDM V core is clocked from the BSCAN when it is enabled, with a clock frequency determined by the JTAG connection.
When programming a System ACE™ device, the MDM V core clock must be at least twice as fast as the System ACE tool controller clock for the ELF file to load correctly.