AXI4-Lite Interfaces - 1.0 English - PG428

Read from a register that does not have all 0s as a default to verify that the interface is functional. Output S_AXI_ARREADY asserts when the read address is valid, and output S_AXI_RVALID asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:

• The S_AXI_ACLK input is connected and toggling.
• The interface is not being held in reset, and S_AXI_ARESETN is an active-Low reset
• If the simulation has been run, verify in simulation and/or a debug feature capture that the waveform is correct for accessing the AXI4-Lite interface.