The following table describes the MDM V core registers accessible through the AXI4-Lite slave interface.
| Register Name | Size (bits) | Address Offset | Access | Description |
|---|---|---|---|---|
| JTAG UART Registers (C_USE_UART = 1) | ||||
| UART_RX_FIFO | 8 | 0x00 | R | JTAG UART receive data |
| UART_TX_FIFO | 8 | 0x04 | W | JTAG UART transmit data |
| UART_STATUS | 8 | 0x08 | R | JTAG UART status |
| UART_CTRL | 8 | 0x0C | W | JTAG UART control |
| Trace Funnel Registers (C_DBG_REG_ACCESS = 1, C_TRACE_OUTPUT = 1, C_MB_DBG_PORTS > 1) | ||||
| trFunnelControl | 4 | 0x1000 | R/W | Trace funnel control register |
| trFunnelImpl | 12 | 0x1004 | R | Trace funnel implementation register |
| trFunnelDisInput | 16 | 0x1008 | R | Disable individual funnel inputs |
| Trace PIB Sink Registers (C_DBG_REG_ACCESS = 1, C_TRACE_OUTPUT = 1) | ||||
| trPibControl | 32 | 0x2000 | R/W | PIB sink control register |
| trPibImpl | 12 | 0x2004 | R | Trace PIB implementation register |
| Trace AXI4-Stream Sink Registers (C_DBG_REG_ACCESS = 1, C_TRACE_OUTPUT = 2) | ||||
| trStreamControl | 32 | 0x2000 | R/W | AXI4-Stream sink control register |
| trStreamImpl | 12 | 0x2004 | R | Trace AXI4-Stream implementation register |
| Trace System Memory Sink Registers (C_DBG_REG_ACCESS = 1, C_TRACE_OUTPUT = 3) | ||||
| trRamControl | 32 | 0x2000 | R/W | RAM Sink control register |
| trRamImpl | 14 | 0x2004 | R | RAM Sink implementation information |
| trRamStartLow | 32 | 0x2010 | R/W | Lower 32 bits of start address of circular trace buffer |
| trRamStartHigh | 0-32 | 0x2014 | R/W | Upper bits of start address of circular trace buffer |
| trRamLimitLow | 32 | 0x2018 | R/W | Lower 32 bits of end address of circular trace buffer |
| trRamLimittHigh | 0-32 | 0x201C | R/W | Upper bits of end address of circular trace buffer |
| trRamWPLow | 32 | 0x2020 | R/W | Lower 32 bits of current write location for trace data |
| trRamWPHigh | 0-32 | 0x2024 | R/W | Upper bits of current write location for trace data |
The JTAG UART registers are identical to the AXI UART Lite registers (see the AXI UART Lite LogiCORE IP Product Guide (PG142)), except that the Status register bits 5–7 (OverrunError, Frame Error, Parity Error) are never set, and the Control register bit 2 is not reserved.
The Trace Funnel Registers and Trace PIB Sink Registers can either be
accessed from the AXI Slave interface (C_DBG_REG_ACCESS = 1) or
from the RISC-V System Bus (C_DBG_REG_ACCESS = 0 and
C_DBG_MEM_ACCESS = 0). The trFunnelDisInput register is
optional, and not implemented in the MDM V.
The MDM V core always responds to accesses within the defined address space. When Parallel Debug Register Access is enabled, the defined address space is 0x000–0x1FF; and when JTAG UART is enabled it is 0x0–0xF. For any unused addresses, write requests are ignored and read requests return zero data.