AXI Slave Register Space - 1.0 English

AXI Slave Register Space - 1.0 English - PG428

MicroBlaze Debug Module V (MDM V) LogiCORE IP Product Guide (PG428)

Document ID

PG428

Release Date

2024-11-13

Version

1.0 English

The following table describes the MDM V core registers accessible through the AXI4-Lite slave interface.

Table 1. MDM V Core AXI4-Lite Slave Registers
Register Name	Size (bits)	Address Offset	Access	Description
JTAG UART Registers (C_USE_UART = 1)
UART_RX_FIFO	8	0x00	R	JTAG UART receive data
UART_TX_FIFO	8	0x04	W	JTAG UART transmit data
UART_STATUS	8	0x08	R	JTAG UART status
UART_CTRL	8	0x0C	W	JTAG UART control

The JTAG UART registers are identical to the AXI UART Lite registers (see the AXI UART Lite LogiCORE IP Product Guide (PG142)), except that the Status register bits 5–7 (OverrunError, Frame Error, Parity Error) are never set, and the Control register bit 2 is not reserved.

The MDM V core always responds to accesses within the defined address space. When Parallel Debug Register Access is enabled, the defined address space is 0x000–0x1FF; and when JTAG UART is enabled it is 0x0–0xF. For any unused addresses, write requests are ignored and read requests return zero data.