| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 |
AMD UltraScale+™ , AMD UltraScale™ , AMD Zynq™ 7000 SoC, 7 series, Versal adaptive SoCs |
| Supported User Interfaces |
BSCAN Interface |
| Provided with Core | |
| Design Files |
Encrypted RTL |
| Example Design |
Not provided |
| Test Bench |
Not provided |
| Constraints File |
XDC |
| Simulation Model |
Not provided |
| Supported S/W Driver 2 |
N/A |
| Tested Design Flows 2 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support | |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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