Clocking - 1.0 English - PG422

This section describes the link clock (rx_lnk_clk), video clock (rx_vid_clk), and Video Bridge to AXI4-Stream master interface clock. When the AXI4-Stream interface is selected for DP RX, the output clock of Video to AXI4-Stream bridge that is m_axis_aclk_stream must be selected such that it is greater than or equal to rx_vid_clk.

The rx_lnk_clk is a link clock input to the DisplayPort 2.1 RX Subsystem generated by the Video PHY (GT).

The following table shows the clock ranges.

The core uses the following clock domains:

lnk_clk

The rxoutclk from the Video PHY is connected to the RX subsystem link clock. Most of the core operates in link clock domain. This domain is based on the lnk_clk_p/n reference clock for the transceivers. The link rate switching is handled by a DRP state machine in the core PHY later. When the lanes are running at 2.7 Gb/s, lnk_clk operates at 67.5 MHz. When the lanes are running at 1.62 Gb/s, lnk_clk operates at 40.5 MHz. When the lanes are running at 5.4 Gb/s, lnk_clk operates at 135 MHz. When the lanes are running at 8.1 Gb/s, lnk_clk operates at 202.5 MHz. When the lanes are running at 10 Gb/s, lnk_clk operates at 312.5 MHz.

In the DisplayPort Sink core, lnk_clk is derived from the recovered clock from the transceiver. When the cable is disconnected this clock becomes unstable.

Note: lnk_clk = link_rate/40 for 8b/10b channel coding link rates and link_rate/32 for 128b/132b channel coding link rates..

rx_dec_clk

This clock is fed to RX subsystem from Video PHY. RX to External Video PHY Lane interface (s_axis_lnk_rx_lanen_*) is driven on this clock domain which operates at link_rate/128. For example, when the lanes are running at 8.1 Gb/s, rx_dec_clk operates at 63.28125 MHz, when the lanes are running at 10 Gb/s, rx_dec_clk operates at 78.125 MHz.

rx_vid_clk

This is the primary user interface clock. Frequency of this clock is dependent on whether "frame buffer" is being used in the design or not as well as if the interface is AXI or Native Mode. If an inaccurate clock is used, the DisplayPort FIFO can overflow or underflow causing data corruption.

AXI Mode with a Frame Buffer

With a frame buffer, rx_vid_clk can run up to 300MHz and must be at least equal to the (pixel clock/Configured PPC).

This is the AMD implemented solution as it does not require any external clock management.

Native Mode or AXI Mode without a Frame Buffer

For non-frame buffer designs, the DisplayPort RX core requires the generation of a video stream using the M and N values within the Main Stream Attributes for 8b/10b channel coding and using VFREQ values within Main Stream Attributes for 128b/132b channel coding to reconstruct an accurate stream clock. The DisplayPort RX core places this information on dedicated signals and provides an update flag to signal a change in these values. The following figure shows how to use the M and N values from the core to generate a clock. For more details, see the VESA DisplayPort Standard (VESA website).

Recommended: The AMD MMCM is not accurate enough to be used to regenerate the necessary clock for non-frame buffer design. You need to use an external PLL that meets the requirements of the DisplayPort standard. For more details, see the VESA DisplayPort Standard (VESA website).

Figure 1. Receiver Clock Generation for 8b/10b channel coding

Note: For 128b/132b channel coding absolute value of receiver clock frequency (VFREQ) is directly transmitted from TX to RX instead of lnk_m_vid, lnk_n_vid (refer to the 0x1608 address description in DisplayPort Registers). Hence, the receiver clock can be generated using this value.

s_axi_aclk

This is the processor domain. It has been tested to run as fast as 135 MHz. The AUX clock domain is derived from this domain, but requires no additional constraints. In an AMD UltraScale™ FPGA, s_axi_aclk clock is connected to a free-running clock input. gtwiz_reset_clk_freerun_in is required by the reset controller helper block to reset the transceiver primitives. A new GUI parameter is added for AXI_Frequency, when the DisplayPort IP is targeted to UltraScale FPGA.

m_aud_axis_aclk

This clock is used by the sink audio streaming interface. It must be = 512 × audio sample rate.

m_axis_aclk_stream<n>

This clock is used to output AXI4-Stream data from the core in the AXI4-Stream mode. This can be of constant frequency (greater than rx_vid_clk) and can run at a maximum frequency of 300 MHz.

For more information on clocking, see the Video PHY Controller LogiCORE IP Product Guide (PG230).