DisplayPort 2.x TX Subsystem Product Guide (PG420) - 1.0 English - PG420

Document ID: PG420
Release Date: 2024-12-18
Version: 1.0 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Core Overview
Unsupported Features
Licensing and Ordering
License Checkers
Product Specification
AXI4-Stream Video Interface
Native Video Interface
Subsystem Sub-Core Descriptions
DisplayPort AXI4-Stream to Video Bridge IP Core
Video Timing Controller IP Core
DisplayPort IP Core
AXI SmartConnect IP Core
Standards
Resource Use
Port Descriptions
AXI4-Lite Interface
AXI4-Stream Interface
Native Video Interface
MST Interface
User Ports
External Video PHY Sideband Status Interface
External Video PHY Clock Interface
External Video PHY Lane n Interface
AUX Signals
Interrupt Interface
Register Space
Video Timing Controller Registers
DisplayPort Registers
Link Configuration Field
Core Enables
Core ID
AUX Channel Interface
Main Stream Attributes
PHY Configuration Status
MST Mode Registers
Designing with the Subsystem
DisplayPort Overview
Main Link Setup and Management
Link Training
Source Core Setup and Initialization
Source Core Setup
On HPD Assertion
Training Pattern 1 Procedure (Clock Recovery) for 8b/10b Channel Coding Link Rates
Training Pattern 2/3/4 Procedure (Symbol Recovery, Interlane Alignment) for 8b/10b Channel Coding Link Rates
Training Pattern for DPTX LANEx_CHANNEL_EQ_DONE for 128B/132B Channel Coding Link Rates
Enabling Main Link Video
Training Pattern for DPTX CDS_DONE for 128B/132B Channel Coding Link Rates
Accessing the Link Partner
AUX Write Transaction
AUX Read Transaction
AUX Channel Command for I2C Transactions
Generation of AUX Transactions
Handling I2C Read Defers/Timeout
Handling I2C Write Partial ACK
Handling I2C Write Defer/Timeout
AUX IO Location
Transmitter Video Clock Generation for 8b/10b Channel Coding Link Rates
Transmitter Video Clock Generation for 128b/132b Channel Coding Link Rates
Hot Plug Detection
HPD Event Handling
Programming the Core in MST Mode
Enabling MST
Payload Bandwidth Management
EDID I2C Speed Control
Pixel Mapping
Pixel Mapping Examples on AXI4-Stream Interface
Pixel Mapping Examples on AXI4-Stream Interface (UG934-Compliant)
Pixel Mapping on Native Video Interface
Pixel Mapping Examples on the User Data Interface
AXI4-Stream Interface Color Mapping
Clocking
Resets
Address Map Example
Physical Layout
Programming Sequence
Design Flow Steps
Customizing and Generating the Subsystem
Subsystem Configuration Screen
User Parameters
Output Generation
Constraining the Subsystem
Synthesis and Implementation
Example Design
Available Example Designs
Building the Example Design
Hardware Setup and Run
Setting the FMC Voltage to 1.8V
Upgrading
Questions and Answers
Driver Documentation
Helper Cores
Audio Video (AV) Pattern Generator (av_pat_gen)
Feature Summary
Port Descriptions
Register Details
Programming sequence:
For Video
Video Frame CRC (video_frame_crc)
Feature Summary
Port Descriptions
Register Details
Functionality
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the DisplayPort 2.x TX Subsystem
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Hardware Debug
General Checks
Transmit – Training Issue
Transmit – Main Link Problem After Training
Transmit – Misaligned Data
Software Debug
Additional Resources and Legal Notices
Support Resources
Finding Additional Documentation
References
Revision History
Please Read: Important Legal Notices

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