|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
Adaptive SoC (AMD Versal™ AI Edge and AMD Versal™ AI Core Series) |
| Supported User Interfaces |
AXI4-Lite, AXI4
|
| Provided with
Core
|
| Design Files |
Encrypted RTL |
| Example Design |
Not Provided |
| Constraints File |
Xilinx Design Constraints File (XDC) |
| Simulation Model |
Not Provided |
| Supported S/W Driver |
Included in PetaLinux |
| Tested Design
Flows
2
|
| Design Entry |
AMD Vivado™
Design Suite |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 000034162
|
| All Vivado IP Change Logs |
Master Vivado IP
Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|