Shared sys_clk Inputs - 1.0 English - PG406

Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)
Document ID
PG406
Release Date
2025-06-03
Version
1.0 English

Two DDRMC5 instances in a common bank triplet, sharing a middle bank can share a single sys_clk input, provided both DDRMC5 instances are of the same type and run at the same data rate. To share a common clock input, change System Clock on the DDR Basic tab from Differential to No Buffer, as shown in the following figure.

Figure 1. System Clock: No Buffer

Tie both sys_clk inputs of the AXI NoC2 instance together, and drive them from an instance of Utility Buffer IP whose input connects to a GC input pin pair in the shared bank, as shown in the following figure.

Figure 2. AXI NoC2 sys_clk inputs Driven from Utility Buffer IP

For no buffer configurations, constraints for system clock are generated in the IP XDC. You must set the IO properties for the system clock in the top-level XDC. Following are sample constraints that need to be added in the top-level XDC as per system clock port names:

  • set_property IOSTANDARD LVDS12 [get_ports {sys_clk_p sys_clk_n}]
  • set_property CTLE_EQ CTLE_EQ_LEVEL7 [get_ports {sys_clk_p sys_clk_n}]
  • set_property PULLTYPE OFF [get_ports sys_clk_p]