Revision History - Revision History - 1.0 English - PG406

Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)
Document ID
PG406
Release Date
2025-12-17
Version
1.0 English

The following table shows the revision history for this document.

Section Revision Summary
12/17/2025 Version 1.0
NoC Methodology Guide Added section.
Address Decoding and the System Address Map
  • Updated DDR_CH0 address region
  • Added note on single NMU access to separate DDR memory controllers.
  • Fixed link to AM026.
  • Removed reference to AM011.
Write Transactions Added note for NMU transactions with WSTRB=0x0.
NoC and Memory Controller Simulation Clarified performance analysis data.
06/03/2025 Version 1.0
Document split Moved DDRMC5 content to Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456).
Document title Changed title to Programmable Network on Chip (NoC2) LogiCORE IP Product Guide.
General updates Updated for expanded Versal NoC2 device support.
03/07/2025 Version 1.0
Initial release. N/A