References - References - 1.0 English - PG406

Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)

Document ID
PG406
Release Date
2025-12-17
Version
1.0 English

These documents provide supplemental material useful with this guide:

  1. Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
  2. Versal Adaptive SoC Technical Reference Manual (AM011)
  3. Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
  4. Versal AI Edge Series Gen 2 and Prime Series Gen 2 Register Reference (AM028)
  5. Versal Adaptive SoC AIE-ML v2 Register Reference (AM029)
  6. Versal AI Edge Series Gen 2 and Prime Series Gen 2 NoC and Integrated Memory Controller NPI Register Reference (AM033)
  7. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
  8. Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)
  9. AMBA AXI4-Stream Protocol Specification (ARM IHI 0051A)
  10. Versal Adaptive SoC PCB Design User Guide (UG863)
  11. Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
  12. Performance AXI Traffic Generator Product Guide (PG381)
  13. Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
  14. Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
  15. Vivado Design Suite: AXI Reference Guide (UG1037)
  16. Versal Adaptive SoC Design Process Documentation
  17. Getting Started with Versal Memory Interfaces
  18. Memory and NoC Tutorials
  19. Obtaining and Verifying Versal Adaptive SoC Memory Pinouts
  20. Versal Architecture and Product Data Sheet: Overview (DS950)