Parallel-XLNOC Top - Parallel-XLNOC Top - 1.0 English - PG406

A parallel-XLNOC top simulation feature is available which disables generation of the <design>_wrapper_sim_wrapper.v file from the user design hierarchy. This wrapper is replaced by a new xlnoc_top module which is created automatically when launching simulation. This module instantiates the xlnoc block and is placed outside the user source design hierarchy as a parallel top in the simulation file set. The functionality of this new parallel-XLNOC top module with regard to the current sim wrapper is unchanged, and it connects the xlnoc ports using Cross Module Reference (XMR) as before.

Enable the feature as follows:

1. Remove the <design>_wrapper_sim_wrapper instantiation from the test bench (or the RTL top). Replace it with the BD wrapper, or the underlying instantiation that the <design>_wrapper_sim_wrapper was calling earlier in the simulation source hierarchy.
2. Set the following project property in the Tcl console:

   set_property "ENABLE_LOGICAL_NOC_TOP" true [current_project]

3. Run the launch_simulation command to execute the new parallel-XLNOC top simulation flow. The command generates the xlnoc_top module and disables the wrapper (if present).

The feature allows propagation of Parameters and System Verilog interfaces from the test bench to the underlying Design Under Test (DUT) hierarchy, and handles mixed-language designs (Verilog, System Verilog, VHDL) efficiently with possible elimination of cross-module errors.