NoC and Memory Controller simulation support is provided with behavioral models in either System Verilog (RTL in GUI) or SystemC (TLM in GUI). The simulation time with SystemC model is much faster but less accurate compared to the System Verilog model. While both the SystemC and System Verilog models can be used to verify functionality, the System Verilog model should be used for performance analysis. Performance includes both bandwidth and latency. Performance analysis using the System Verilog model is within +/- 5% of hardware. All supported memory densities can be simulated using the System Verilog model.
The System Verilog model is a behavioral model developed for performance analysis. Not all memory controller features are modeled. For a complete list of unmodeled features, refer to the Simulation section of Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456).