The following figure is a representation of the NoC. It shows how various elements are connected to construct a NoC system and how the NoC is incorporated within the device.
As shown, the NoC system is a large-scale interconnection of instances of NoC master units (NMUs), NoC slave units (NSUs), and NoC packet switches (NPSs), each controlled and programmed from a NoC programming interface (NPI).
The AMD Versal™ Programmable NoC is statically routed by AMD Vivado™ software at design time. That is, the assignment of NoC ingress and egress points to specific NMUs and NSUs and the routing paths to implement connections between ingress and egress are computed at design time by the NoC compiler, part of the AMD Vivado™ Design Suite. The NoC compiler considers the connectivity of the design and quality of service constraints supplied by the designer to solve for a globally optimal solution. This solution is then expressed as configuration data in the final application PDI files.
The NoC and DDRMC5 system must be configured/programmed from the NPI at early boot and be ready before NoC data paths or DDRMC5 are used. The NPI programs NoC and DDRMC5 registers that define the routing table, rate modulation, QoS configuration, and timing parameters. Programming of the NoC and DDRMC5 from the NPI requires no user intervention, it is fully automated and executed by the platform management controller (PMC). For more information about boot and configuration refer to the Versal Adaptive SoC Technical Reference Manual (AM011) and the Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).