NMU128 (Low Latency) - 1.0 English - PG406

Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)

Document ID
PG406
Release Date
2025-06-03
Version
1.0 English

The NMU128 is optimized for the low latency requirements of hardened blocks such as the PS. The NMU128 has a fixed 128-bit AXI data width. It does not support the AXI4-Stream protocol and does not support master-defined destination IDs. Otherwise, it supports all of the features of the NMU512.