The NMU supports interleaving memory transactions across two, four, or eight hardened memory controller channels. The memory regions can be programmed to be interleaved at a granularity of 64 bytes to 4 KBytes, or can be programmed to disable interleaving. The choice of whether to interleave, the interleave granularity, and the address of the interleaved region are determined at the time the NoC is configured.
When configured to support interleaved memory controller channels, the NMU is configured to stripe transactions bound for the DDR across the two, four, or eight memory controller channels as follows:
- The transaction is chopped into smaller packets to align with the memory space of each physical channel. Packet chopping occurs on the interleave boundary between each memory channel.
- Each sub-packet is addressed separately to the correct physical DDR controller. In dual-channel mode, each channel is assigned to one of the two memory controller ports, and the sub-packet is addressed to the correct port.
- Responses are re-assembled at the NMU and returned to the attached master.