|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™ AI Edge Series Gen
2,
Versal Prime Series Gen 2, Versal Prime VM2152 device, Versal Premium Series Gen 2, Versal RF Series
|
| Supported User Interfaces |
AXI3, AXI4, and AXI4-Stream
|
| Provided with Core
|
| Design Files |
RTL |
| Example Design |
N/A |
| Test Bench |
Verilog |
| Constraints File |
XDC |
| Simulation Model |
SystemVerilog, SystemC |
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
AMD Vivado™
IP
Integrator |
| Simulation |
Mentor Graphics Questa Advanced Simulator, Cadence Xcelium
Parallel Simulator, Synopsys VCS. |
| Synthesis |
AMD Vivado™
Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 75764
|
| All Vivado IP Change Logs |
Master Vivado IP
Change Logs: 72775
|
|
Support web page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|