Each DDR memory controller has a partial NSU (DDRMC5-NSU) for each port. The DDRMC5-NSU serves to convert from the NoC packet domain to the memory controller domain without first converting to AXI protocol.
Each DDR memory controller has a partial NSU (DDRMC5-NSU) for each port. The DDRMC5-NSU serves to convert from the NoC packet domain to the memory controller domain without first converting to AXI protocol.