The NoC is clocked by a single clock for the entire chip. The NMUs/NSUs have asynchronous integrated FIFOs to ensure transition from the AXI clock domain of an individual master or slave to the NoC clock domain.
The NoC clock is controlled by a PLL inside the PS IP. To Change the NoC Clock Frequency the PS IP must be opened and used. This can be done using a Tcl command or via the GUI as shown in the following figure.
For more details about the NPLL refer to the Clocks chapter in the Versal Adaptive SoC Technical Reference Manual (AM011) and the Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026) .
| Clock | Description |
|---|---|
| aclkn | The AXI NoC and AXIS NoC IP can be configured to have up to N independent AXI clocks, where N is the sum of the number of AXI interfaces on the IP core. |
| sys_clk | If an instance of axi_noc2
is configured to include an integrated DDRMC5, one sys_clk port appears on the boundary of the IP for each DDRMC5. This port
must be connected to a differential clock source whose frequency is user-selectable on
the DDR Basic tab of the AXI NoC DDRMC5
configuration dialog. To access the DDR Basic tab, click Configure DDRMC5 on the DDRMC5
Configuration tab of the AXI NoC2 configuration dialog. The
sys_clk differential clock source must be placed on a predetermined global clock (GC)
pair output by the Vivado tools as per the selected configuration. This clock is used
internally by the DDRMC5 to generate various clocks for the controller and external
DDR memory. Alternatively, two DDRMC5 instances in a common bank triplet can share a single sys_clk input, as described below. For information on clocking, refer to the Clocking section of the Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456) and Answer Record 000037912 - Versal Gen 2 Adaptive SoC DDRMC5 - Memory Controller Clocking Guidelines for Differential, No Buffer, and Internal HSM1 Options. |