The AMD Versal™ adaptive SoC programmable NoC system address map defines the default address locations of slaves in the Versal device. The address map is built into the integrated interconnect of the NoC. The NoC provides some capabilities to perform address re-mapping which allow the address map to be customized to the target application.
Address Regions
- DDR CH0
- Address region DDR CH0 comprises multiple sub-regions: DDR CH0 LEGACY, DDR
CH0 MED, DDR CH0 HIGH 0, and DDR CH0 HIGH 1, totaling 1 TB of space. The low
2 GB of that space, DDR CH0 LEGACY, is addressable by 32-bit address
masters. Address regions DDR CH1, DDR CH1A, DDR CH2, DDR CH2A, DDR CH3, DDR
CH3A, and DDR CH4 each can map to independent memory controllers.Note: A single NMU cannot access separate DDR memory controllers in the same address region unless they are interleaved. For purposes of this restriction, all of DDR CH0 is considered one address region. So for example, it is not possible to have an NMU access one DDRMC5 in DDR CH0 LEGACY and another DDRMC5 in DDR CH0 MED. The higher address regions, DDR CH1, DDR CH1A, etc. are all considered separate regions.
- PS
- The various PS slave regions (LPD_AFI_FS, FPD_AFI_0, FPD_AFI_1, QSPI, PCIe_0, PMC, STM_CORESIGHT, CPMx, FPD_SLAVES, and LPD_SLAVES) have fixed address regions within the low 4 GB of the address space to allow for access by 32-bit masters.
- PMC_ALIAS
- The PMC_ALIAS regions provide access to the address space of the PMC block in one SLR from masters in other SLRs. For example, access to the PMC in SLR1 from SLR0 would be through the PMC_ALIAS_1 address region.
- PS_to_PL
- The PS_to_PL address region provides direct access from masters in the PS to slaves in the PL through the AFI interface. This region is not accessible from the NoC.
- PL_LO and PL_HI
- The PL_LO, and PL_HI regions do not have dedicated address decoders.
Transactions to these regions must use the fixed destination ID, a master
defined destination ID, or an address remap register.
If a transaction is being routed using the AXI address and the incoming address does not hit in any address matcher or fall in the PL_LO or PL_HI spaces, an AXI DECERR is generated and an interrupt status bit is set to indicate an address map error. Transactions that fall in the PL_LO or PL_HI spaces but do not hit in a remap register and hence do not receive a valid destination ID can still be injected into the NoC routing fabric. In this case an NSU can be configured as an error slave to receive such invalid transactions. The error slave is configured to return a DECERR instead of a SLVERR.