TUSER Field Packing (s_axis_din_tuser, m_axis_dout_tuser) - TUSER Field Packing (s_axis_din_tuser, m_axis_dout_tuser) - 1.1 English - PG401

RFSoC DFE Non-Linear Filter LogiCORE IP Product Guide (PG401)
Document_ID
PG401
Release_Date
2026-06-23
Version
1.1 English

s_axis_din_tuser

The core receives the external index and LUT bank select information through the s_axis_din_tuser bus. The total width of the tuser is determined by the number of phases and the format is as shown in the following table.

Note: The LUT bank select information from the tuser bus is used only when the PP_LUT_MODE = Delay line control. In delay line control mode, LUT memories/banks switch over at different instances and they are dependent on the propagation through the delay line.
Table 1. s_axis_din_tuser Format
PH3 PH2 PH1 PH0
LUT Bank select Index LUT Bank select Index LUT Bank select Index LUT Bank select Index
39 37-30 29 27-20 19 17-10 9 7-0

You can input a custom index through the s_axis_din_tuser bus in the external indexing mode in the DFE NLF IP core. This gives you more flexibility in using application-specific or proprietary indexing patterns. Unlike the default modulus-based indexing (abs(x(n))), external indexing can accommodate alternate patterns, such as abs(x^2(n)), thus allowing more complex transformations. When two 16x16 grids are placed non-diagonally, external indexing enables precise access by directly addressing the LUTs regardless of their grid position. The FABRIC_INDEX_SELECT register dynamically controls the indexing mode. This allows seamless switching between modes, thus enhancing control and versatility for a range of signal processing applications.

m_axis_dout_tuser

m_axis_dout_tuser provides the output overflow status. The width of the tuser is determined by the number of phases.

Table 2. m_axis_dout_tuser Format
PH3 PH2 PH1 PH0
overflow_real overflow_imag overflow_real overflow_imag overflow_real overflow_imag overflow_real overflow_imag
13 12 9 8 5 4 1 0