After generating the test cases, the next step is to run the Vivado simulation. Inside each test case directory, there is a vivado_dir_1 directory containing a run_sim.tcl file and a dfe_nlf_v1_1_tb.vhd file.
When the run_sim.tcl file is sourced to the Vivado Design Suite, it creates a Vivado project targeting the AMD Zynq™ UltraScale+™ RFSoC-DFE device [xczu67dr-ffve1156-2-i]. It initializes the IP parameters to the corresponding parameters entered through MATLAB and runs a behavioral simulation for the test case.
The shell script vivado_batch_scr.sh demonstrates how to automate Vivado runs in the Linux OS. Assume the server uses clustered LSF, and Vivado runs in batch mode. For more details, refer to the following documents:
- Vivado Design Suite User Guide: Logic Simulation (UG900)
- Vivado Design Suite Quick Reference Guide (UG975)
The Vivado simulation generates the data_out_rtl.txt file and the side_info.txt file. The script cosim_analyze_hdl_perf.m uses these files to analyze the results.
