The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 06/23/2026 Version 1.1 | |
| Performance | Added Delay Line Output Latency section. |
| Output Data Fixed-Point Format | Added section. |
| 11/20/2025 Version 1.1 | |
| Product Specification | Corrected offset addresses for the following registers in Memory Address Map.
|
| 05/29/2025 Version 1.1 | |
| Overview |
|
| Product Specification | Updated information in the "Module Select" column in Memory Address Map |
| Designing with the Core |
|
| Design Flow Steps | Updated GUI image in Configuration Tab |
| Co-Simulation User Guide | Updated figures in Generating the Co-Sim Test Vectors |
| 05/30/2024 Version 1.1 | |
| Initial release. | N/A |