Resets - Resets - 1.1 English - PG401

The following resets are available:

s_axi_ctrl_aresetn

The AXI4-Lite control interface has its own dedicated reset, s_axi_ctrl_aresetn, and this must be synchronous to s_axi_ctrl_aclk.

It resets all AXI4-Lite interface logic and prevents any communication on the control interface. Hence, you must only apply it when the control interface has no pending transactions.

aresetn

All reset signals have active-Low sensitivity. In the design, aresetn is the main reset. It must be synchronous to aclk.

Use aresetn to reset all system logic. When you assert aresetn, the system immediately disables the output data. The system also disables access to the control AXI4-Lite interface. The core still responds to write and read with dummy responses when the core is under aresetn.