This chapter describes the reference design for the RFSoC DFE Non-Linear Filter IP. A full reference design is available. It allows synthesis and implementation for an AMD ZCU670 evaluation board. The files are located in the refd subdirectory of the DFE_NLF_IP_Reference_Design_v1_1_0.zip archive file with the following directory structure.
- refd/
- IP reference design top level directory.
- hw_flow/
- Hardware build directory
- sw_flow/
- Software build directory
- Makefile
- Script to generate reference design
- Readme.txt
- Readme file for generating reference design
The Reference Design Overview shows the procedure to integrate the RFSoC DFE Non-Linear Filter IP with neighboring DFE subsystem blocks on the RFSoC DFE device family. It is built using AMD Vivado™ tools. Refer to Generating the IP Reference Design for details on building the design.