Performance - Performance - 1.1 English - PG401

RFSoC DFE Non-Linear Filter LogiCORE IP Product Guide (PG401)
Document_ID
PG401
Release_Date
2026-06-23
Version
1.1 English

Latency

The latency of the core depends primarily on the following factors:

  • Super sampling rate (NUM_PHASES)
  • Mode of operation: 32-terms (single grid) or 64-terms (double grid)
  • Indexing mode: internal or external indexing mode

The following table shows the latency of the core in clock cycles. This is measured from input s_axis_din_tvalid to output m_axis_dout_tvalid.

Table 1. Latency
NUM_PHASES 32/64 Terms NUM_NLFs Latency
Internal Indexing External Indexing
1 32 1 23 17
2 32 1 17 11
3 32 2 24 18
4 32 2 18 12
1 64 2 26 20
2 64 2 20 14

Delay Line Output Latency

The following tables show the latency in samples from the input s_axis_din_tvalid to the delay line output valid signals (m_axis_signal_dl_tvalid and m_axis_index_dl_tvalid). There are two delay lines: a signal delay line and an index delay line. The index delay line latency depends on the indexing mode (internal or external). The latency depends on the tap value programmed in the corresponding tap select register and the core configuration.

Sample Delay = T + C

Where T is the tap value programmed in the tap select register (SIGNAL_TAP_SELECT or INDEX_TAP_SELECT) and C is a fixed offset that depends on the configuration, as given in the tables below.

Note: The latency values in the following tables are derived from behavioral simulation results.

Tap select register: SIGNAL_TAP_SELECT (NLF1 offset 0x48–0x49, NLF2 offset 0x48–0x49). The latency formula is: Sample Delay = T + C.

Table 2. Signal Delay Line Output Latency (m_axis_signal_dl_tdata)
NUM_PHASES Grid Sample Delay Formula Valid Tap Range (T)
1 Single T + 12 3–18
2 Single T + 23 2–18
3 Single T + 42 1–18
4 Single T + 57 0–18
1 Double T + 14 3–18
2 Double T + 27 2–18

Tap select register: INDEX_TAP_SELECT (NLF1 offset 0x4A–0x4B, NLF2 offset 0x4A–0x4B). Applicable when FABRIC_INDEX_SELECT = 0 (internal indexing mode).

Table 3. Index Delay Line Output Latency — Internal Indexing Mode (m_axis_index_dl_tdata)
NUM_PHASES Grid Sample Delay Formula Valid Tap Range (T)
1 Single T + 8 3–18
2 Single T + 19 2–18
3 Single T + 36 1–18
4 Single T + 49 0–18
1 Double T + 10 3–18
2 Double T + 23 2–18

Tap select register: INDEX_TAP_SELECT (NLF1 offset 0x4A–0x4B, NLF2 offset 0x4A–0x4B). Applicable when FABRIC_INDEX_SELECT = 1 (external indexing mode).

Table 4. Index Delay Line Output Latency — External Indexing Mode (m_axis_index_dl_tdata)
NUM_PHASES Grid Sample Delay Formula Valid Tap Range (T)
1 Single T + 2 3–18
2 Single T + 7 2–18
3 Single T + 18 1–18
4 Single T + 25 0–18
1 Double T + 4 3–18
2 Double T + 11 2–18
Note: Internal and external indexing mode latencies for the index delay line are not directly comparable. Internal indexing includes the additional CORDIC magnitude computation pipeline latency. Compare delays only by using tap value deltas within the same configuration and indexing mode.
Note: Double grid configurations (NUM_NLFs = 2 with NUM_PHASES = 1 or 2) support both single-grid and double-grid operation. Three-phase and four-phase configurations always use double NLF blocks in single-grid mode.