NL Unit Overview - NL Unit Overview - 1.1 English - PG401

The NLF block contains 16 non-linear (NL) units, each capable of processing two terms, allowing for up to 32 terms per block. Each NL unit features:

LUT0 and LUT1

Configurable LUTs for defining data transformations. The LUTs support high-speed reloading, enabling real-time adaptability.

Delay line taps

Each NL unit connects to the signal and index tapped delay lines, with SIGNAL_SELECT and INDEX_SELECT registers for specifying delay taps based on the unit’s placement within the 16x16 grid.

These NL units process 16-bit I/Q data with 34-bit output precision, enabling high-accuracy transformations. After computation, the system combines the outputs through a summing network after computation. It then scales and rounds them to produce a final 25-bit I/Q output. This output supports high-speed processing for applications requiring low-latency transformations.

The XDFE_NLF IP block also offers advanced configuration for indexing and delay management:

Indexing modes

Set indexing to either an internally generated 8-bit signal magnitude or an external proprietary index through the s_axis_din_tuser bus. You can dynamically adjust the indexing mode using the FABRIC_INDEX_SELECT register.

Tapped delay output

You can access the tapped delay line outputs on the m_axis_signal_dl_tdata and m_axis_index_dl_tdata ports. Configuring these outputs using the DL_OUT_EN, SIGNAL_TAP_SELECT, and INDEX_TAP_SELECT registers.