Memory Address Map - Memory Address Map - 1.1 English - PG401

RFSoC DFE Non-Linear Filter LogiCORE IP Product Guide (PG401)
Document_ID
PG401
Release_Date
2026-06-23
Version
1.1 English
Table 1. Memory Address Map
Module Select Offset Register Name Data Width (bit) Default Value Access Type Description
0x0 0x02 LUT Bank Switch 2 0 RW Bit-1 to set LUT bank switch mode (0=fabric control, 1=register control).

In fabric control mode, the LUT bank select input port switches between PING PONG memories.

In register control mode, bit-0 selects PING PONG memories (0= PONG, 1=PING).

  • Bit-1: LUT bank switch mode (0=fabric control, 1=register control)
  • Bit-0: LUT bank switch (0= PONG, 1=PING)

This register has no effect on LUT bank switching of NLF1/NLF2, when NLF1/NLF2 PP_LUT_MODE = Delay line control.
0x0 0x03 LUT Write Broadcast 1 0 RW When bit-0 is enabled, LUT writes are broadcast to both NLFs. This feature is available in both LUT interface modes.

The typical use case of broadcast is to write same LUT values to both NLFs for three-phase or four-phase designs.

0x0 0x04 Overflow Status 8 0 RO
  • Bit-6: NLF2 CORDIC overflow status
  • Bit-5: NLF2 real (I) output overflow status
  • Bit-4: NLF2 imaginary (Q) output overflow status
  • Bit-2: NLF1 CORDIC overflow status
  • Bit-1: NLF1 real (I) output overflow status
  • Bit-0: NLF1 imaginary (Q) output overflow status
0x0 0x05 Clear Overflow Status 2 0 WO When bit-0 is enabled, NLF1 overflow status is cleared.

When bit-1 is enabled, NLF2 overflow status is cleared.

This register is auto-cleared after one clock cycle of aclk.
0x0 0x06 Cascade Output Bit select 1 0 RW Selects output bits. This is applicable only for the double grid configurations with NUM_PHASES = 1 or 2 and NUM_NLFs = 2.
  • Bit-0 = 0 : output = saturate (NLF1_output + NLF2_output)
  • Bit-0 = 1 : output = floor ((NLF1_output + NLF2_output)/2)

Used to increase the dynamic range of output.
0x0 0x08 NLF IP Version 12 0x102 RO
  • [3:0] : Rev
  • [7:4] : Minor
  • [11:8] : Major
0x0 0x09 HW Configuration 12 - RO
  • [3:0] : NUM PHASES (1/2/3/4)
  • [7:4] : LUT_AXIS_EN (0/1)
  • [11:8] : NUM_NLFs (1/2)
0x0 0x10 Programmable Signal Delay 5 0 RW The programmable signal delay to NLF2 with respect to NLF1. This is applicable only for double grid configurations with NUM_PHASES = 1 or 2 and NUM_NLFs = 2.

Depending on the column/horizontal distance (signal delay) between the two grids, the NLF2 input signal has to be delayed. Use this register to set that delay.
0x0 0x11 Programmable Index Delay 5 0 RW The programmable index delay to NLF2 with respect to NLF1. This is applicable only for double grid configurations with NUM_PHASES = 1 or 2 and NUM_NLFs = 2.

Depending on the row/vertical distance (index delay) between the two grids, the NLF2 input index has to be delayed. Use this register to set that delay.
0x0 0x41 NLF1 LUT Target 20 0 RW Selects the target LUT in NLF1. This is applicable only when the LUT access is through AXI4-Lite (LUT_AXIS_EN=0).
  • [19:16] : NL UNIT ID(3:0) (0=UNIT0, 1=UNIT1, .., F=UNIT15)
  • [15:9] : Reserved
  • Bit-8 : LUT ID (0= LUT0, 1= LUT1)
  • [7:0] : LUT ADDR(7:0)

Each LUT has 256 values, which are addressed using LUT address (7:0). Program this register to select the LUT and the LUT address for the selected LUT to write LUT data to that location using the NLF1 LUT data register.

Internally two LUT addresses are maintained, one (NLF1_LUT_Addr_wr) for writing LUT data and the other (NLF1_LUT_Addr_rd) for reading LUT data using the LUT data register. Writing this register loads both NLF1_LUT_Addr_wr, NLF1_LUT_Addr_rd with LUT ADDR(7:0).

NLF1_LUT_Addr_wr is incremented after each write to the NLF1 LUT data register. You can write 256 LUT values, without writing the NLF1 LUT target register for each LUT data write. NLF1_LUT_Addr_wr wraps up after reaching 255.

NLF1_LUT_Addr_rd is incremented after each read from the NLF1 LUT data register. You can read 256 LUT values, without writing the NLF1 LUT target register for each LUT data read. NLF1_LUT_Addr_rd wraps up after reaching 255.

The read back of this register gives the NLF1 LUT target with current NLF1_LUT_Addr_rd.
0x0 0x42 NLF1 LUT Data 32 0 RW Data input to LUT which is written into the current LUT address (NLF1_LUT_Addr_wr) location of target LUT of NLF1. This is applicable only when LUT access is through AXI4-Lite (LUT_AXIS_EN=0).
  • [31:16] : Two's complement imaginary LUT data
  • [15:0] : Two's complement real LUT data

Auto-increment of the LUT address (NLF1_LUT_Addr_wr) after each LUT data write avoids writing the LUT target register for each LUT data write. After writing the LUT target once, you can write 256 LUT values.

The register read gives LUT data of current LUT address (NLF1_LUT_Addr_rd) location of NLF1 LUT target.

Auto-increment of the LUT address (NLF1_LUT_Addr_rd) after each LUT data read avoids writing LUT target register for each LUT data read. After writing the LUT target once, you can read 256 LUT values.

If you want to write/read LUT data from a particular address of a particular LUT of NLF1, write the NLF1 LUT target register first, then write/read the NLF1 LUT data register.

0x0 0x81 NLF2 LUT Target 20 0 RW Selects the target LUT in NLF2. This is applicable only when LUT access is through AXI4-Lite (LUT_AXIS_EN=0).
  • [19:16] : NL UNIT ID(3:0) (0=UNIT0, 1=UNIT1, .., F=UNIT15)
  • [15:9] : Reserved
  • Bit-8 : LUT ID (0= LUT0, 1= LUT1)
  • [7:0] : LUT ADDR(7:0)

Each LUT has 256 values, which are addressed with LUT address(7:0). Program this register to select the LUT and the LUT address for the selected LUT to write the LUT data to that location using NLF2 LUT data register.

Internally two LUT addresses are maintained, one (NLF2_LUT_Addr_wr) for writing LUT data, and the other (NLF2_LUT_Addr_rd) for reading LUT data using LUT data register. Writing this register loads both NLF2_LUT_Addr_wr, NLF2_LUT_Addr_rd with LUT ADDR(7:0).

NLF2_LUT_Addr_wr is incremented after each write to NLF2 LUT data register. This feature allows you to write 256 LUT values, without writing NLF2 LUT target register, for each LUT data write. NLF2_LUT_Addr_wr wraps up after reaching 255.

NLF2_LUT_Addr_rd is incremented after each read from NLF2 LUT data register. This feature allows you to read 256 LUT values, without writing NLF2 LUT target register, for each LUT data read. NLF2_LUT_Addr_rd wraps up after reaching 255.

The read back of this register gives the NLF2 LUT target with current NLF2_LUT_Addr_rd.
0x0 0x82 NLF2 LUT Data 32 0 RW Data input to LUT which is written into the current LUT address (NLF2_LUT_Addr_wr) of the target LUT in NLF2. This is applicable only when LUT access is through AXI4-Lite (LUT_AXIS_EN=0).
  • [31:16] : Two's complement imaginary LUT data
  • [15:0] : Two's complement real LUT data

Auto-increment of LUT address (NLF2_LUT_Addr_wr) after each LUT data write avoids writing the LUT target register for each LUT data write. After writing LUT target once, you can write 256 LUT values.

Reading this register gives the LUT data of the current LUT address (NLF2_LUT_Addr_rd) of NLF2 LUT target.

Auto-increment of LUT address (NLF2_LUT_Addr_rd) after each LUT data read avoids writing LUT target register for each LUT data read. After writing the LUT target once, you can read 256 LUT values.

If you want to write/read LUT data from a particular address of a particular LUT of NLF2, first write the NLF2 LUT target register, then write/read NLF2 LUT data register.
0x1 0x01 NLF1 UNIT_EN 16 0 RW Enables each NL unit of NLF1.
  • Set bit-0 to 1 to enable NL unit 0
  • Set bit-1 to 1 to enable NL unit 1
  • Set bit-15 to 1 to enable NL unit 15
0x1 0x02 NLF1 PP_LUT_MODE 1 0 RW Sets the PING PONG LUT switch mode for NLF1. This is broadcast to all NL units of NLF1.
  • Bit-0 : 0 = Direct fabric control
  • Bit-0 :1 = Delay line control

In direct fabric control, the PING PONG switching is done either using the LUT_bank_select input port or the LUT_bank_switch register based on the LUT_bank_switch_mode.

In delay line control, the switching is done using lut_bank_sel bit of s_axis_din_tuser.
0x1 0x03 to 0x12 NLF1 SIGNAL_SELECT 16 0 RW Selects signal from delay line for processing for each NL unit of NLF1. One register per unit.
  • [4:0] : Signal Delay Line Tap for Phase 0
  • [12:8] : Signal Delay Line Tap for Phase 1

For the one-phase design, the valid values for the signal delay line tap are 3 to 18.

For the two-phase design, the valid values for the signal delay line tap are 2 to 18 (includes one sample delay from phase0 to phase1 of two-phase input signal).

For the three-phase design, the valid values for signal delay line tap are 1 to 18 (includes two sample delay from phase0 to phase2 of three phase input signal).

For the four-phase design, the valid values for the signal delay line tap are 0 to 18 (includes three sample delay from phase0 to phase3 of four phase input signal).
0x1 0x23 to 0x32 NLF1 INDEX_SELECT 32 0 RW Selects index from the delay line for processing for each NL unit of NLF1. One register per unit.
  • [4:0] : Selects index delay line tap for LUT0 phase 0
  • [12:8] : Selects index delay line tap for LUT0 phase 1
  • [20:16] : Selects index delay line tap for LUT1 phase 0
  • [28:24] : Selects index delay line tap for LUT1 phase 1

For the one-phase design, the valid values for the index delay line tap are 3 to 18.

For the two-phase design, the valid values for the index delay line tap are 2 to 18 (includes 1 sample delay from phase0 to phase1 of two phase input signal).

For the three-phase design, the valid values for the index delay line tap are 1 to 18 (includes 2 sample delay from phase0 to phase2 of three phase input signal).

For the four-phase design, the valid values for the index delay line tap are 0 to 18 (includes 3 sample delay from phase0 to phase3 of four phase input signal).
0x1 0x43 NLF1 DL_OUT_EN 1 0 RW Enables internal delay line outputs to fabric.
0x1 0x44 NLF1 PRE_ADD_EN 16 0 RW Enables pre-addition for each NL unit of NLF1. One bit per unit.

If pre_addition is enabled, the output of the unit = signal X (LUT0[LUT0_INDEX] + LUT1[LUT1_INDEX])

If pre_addition is disabled, the output of the unit = signal X (LUT0[LUT0_INDEX] )
0x1 0x45 NLF1 SHIFT_MODE 2 0 RW Sets NLF1 delay line shift mode. The shift mode depends on the NUM_PHASES. SHIFT_MODE must be NUM_PHASES-1.
0x1 0x46 NLF1 OUT_SCALE 4 0 RW NLF1 output scaling factor applied before saturation and rounding. NLF1 output is left shifted by the OUT_SCALE number of bits. Valid range of values is 0 to 12.
0x1 0x47 NLF1 FABRIC_INDEX_SELECT 1 0 RW Selects the fabric as the index source instead of the absolute value of the signal for NLF1.

If this register is set, the index bits of s_axis_din_tuser are used as the fabric index for NLF1.
0x1 0x48 to 0x49 NLF1 SIGNAL_TAP_SELECT 5 0 RW Selects NLF1 signal delay line tap for fabric output. One register for each phase.
  • For one-phase design, the valid range of values are 3 to 18.
  • For two-phase design, the valid range of values are 2 to 18.
  • For three-phase design, the valid range of values are 1 to 18.
  • For four-phase design, the valid range of values are 0 to 18.

This register is active when DL_OUT_EN is enabled.
0x1 0x4A to 0x4B NLF1 INDEX_TAP_SELECT 5 0 RW Selects NLF1 index delay line tap for fabric output. One register for each phase.
  • For one-phase design, the valid range of values are 3 to 18.
  • For two-phase design, the valid range of values are 2 to 18.
  • For three-phase design, the valid range of values are 1 to 18.
  • For four-phase design, the valid range of values are 0 to 18.

This register is active when NLF1 DL_OUT_EN is enabled.
0x2 0x01 NLF2 UNIT_EN 16 0 RW Enables each NL unit of NLF2.
  • Set bit-0 to 1 to enable unit0
  • Set bit-1 to 1 to enable unit1
  • Set bit-15 to 1 to enable unit15
0x2 0x02 NLF2 PP_LUT_MODE 1 0 RW Sets the PING PONG LUT switch mode for NLF2. This is broadcast to all NL units of NLF2.
  • Bit-0 : 0 = Direct fabric control
  • Bit-0 : 1 = Delay line control in direct fabric control

The PING PONG switching is done either using LUT_bank_select input port or the LUT_bank_switch register based on LUT_bank_switch_mode.

In delay line control, switching is done using lut_bank_sel bits of s_axis_din_tuser.
0x2 0x03 to 0x12 NLF2 SIGNAL_SELECT 16 0 RW Selects signal from delay line for processing for each NL unit of NLF2. One register per unit.
  • [4:0] : Signal delay line tap for phase 0
  • [12:8] : Signal delay line tap for phase 1

Valid range of values of signal delay line tap are 0 to 18 as explained in the NLF1 SIGNAL SELECT register description.
0x2 0x23 to 0x32 NLF2 INDEX_SELECT 32 0 RW Selects index from delay line for processing for each NL unit of NLF2. One register per unit.
  • [4:0] : Selects index delay line tap for LUT0 phase 0
  • [12:8] : Selects index delay line tap for LUT0 phase 1
  • [20:16] : Selects index delay line tap for LUT1 phase 0
  • [28:24] : Selects index delay line tap for LUT1 phase 1

Valid range of values of index delay line tap are 0 to 18 as explained in the NLF1 INDEX SELECT register description.
0x2 0x43 NLF2 DL_OUT_EN 1 0 RW Enables NLF2 delay line outputs to fabric.
0x2 0x44 NLF2 PRE_ADD_EN 16 0 RW Enables pre-addition for each NL unit. One bit per unit.

If pre_addition is enabled, the output of the unit = signal X (LUT0[LUT0_INDEX] + LUT1[LUT1_INDEX])

If pre_addition is disabled, the output of the unit = signal X (LUT0[LUT0_INDEX] )
0x2 0x45 NLF2 SHIFT_MODE 2 0 RW Sets the delay line shift mode for NLF2. The shift mode depends on the NUM_PHASES. SHIFT_MODE must be NUM_PHASES-1.
0x2 0x46 NLF2 OUT_SCALE 4 0 RW NLF2 output scaling factor applied before saturation and rounding. NLF2 output is left shifted by the OUT_SCALE number of bits.

Valid range of values is 0 to 12.
0x2 0x47 NLF2 FABRIC_INDEX_SELECT 1 0 RW Selects the fabric as the index source instead of the absolute value of the signal for NLF2. If this register is set, the index bits of s_axis_din_tsuser are used as the fabric index.
0x2 0x48 to 0x49 NLF2 SIGNAL_TAP_SELECT 5 0 RW Selects the NLF2 signal delay line tap for fabric output. One register for each phase. Valid range of values are 0 to 18 as explained in the NLF1 SIGNAL_TAP_SELECT register description.

This register is active when NLF2 DL_OUT_EN is enabled.
0x2 0x4A to 0x4B NLF2 INDEX_TAP_SELECT 5 0 RW Selects the NLF2 index delay line tap for fabric output. One register for each phase. Valid range of values are 0 to 18 as explained in the NLF1 INDEX_TAP_SELECT register description.

This register is active when NLF2 DL_OUT_EN is enabled.