Low Power Mode - Low Power Mode - 1.1 English - PG401

To keep the core in low power mode when not in use, deassert enable. When enable is Low, the system suspends all activity except for the configuring registers (not LUTs) through the AXI4-Lite interface.

The following procedure describes how to set up the IP for Time Division Multiplexing (TDD) power saving mode.

1. When TDD UL period has started, deassert s_axis_lut_config_tvalid to disable any further LUT memory transactions in case of LUT access through AXI4-Stream. Wait until the AXI4-Lite completes any LUT memory transaction, whether it is a read or write.
2. Set s_axis_din_tdata to zero while s_axis_din_tvalid is High for datapath latency cycles to flush the data.
3. Wait for m_axis_dout_tvalid to go Low and deassert enable to enter power saving mode.
4. If necessary, re-configure the registers but not the LUTs.
5. Complete the TDD UL period, then assert enable to enter operational mode.

After one clock cycle, the core is ready to accept transactions on s_axis_lut_config or s_axis_din interfaces.