LUT Bank Switching in Direct Fabric Control Mode - LUT Bank Switching in Direct Fabric Control Mode - 1.1 English - PG401

RFSoC DFE Non-Linear Filter LogiCORE IP Product Guide (PG401)
Document_ID
PG401
Release_Date
2026-06-23
Version
1.1 English

You can switch between RAMs (banks) by programming the LUT_BANK_SWITCH register or through the lut_bank_select input of the IP. The switch over mode is runtime selectable using the LUT_BANK_SWITCH_MODE register.

Table 1. PING_PONG_RAM_SEL
LUT_BANK_SWITCH_MODE LUT_BANK_SWITCH Register lut_bank_select Port New Write Operation is Performed onto PING/PONG RAMs
0 x 0 PONG
0 x 1 PING
1 0 x PONG
1 1 x PING

After writing all LUTs into the PONG RAM, write operations can be switched to the PING RAM. The core then reads the latest updated LUTs from the PONG RAM and vice versa. This switching is done in a single clock cycle for all the LUTs. The RFSoC DFE Non-Linear Filter IP output also switches to the new LUT bank in a single clock cycle after some latency. The latency depends on the IP configuration.

The following figure shows the output switching latency in case of LUT_BANK_SWITCH_MODE = 0. It is the latency from switching the lut_bank_select port to the switching of the NLF IP output to the LUT bank selected for read operation.

Figure 1. Output Switch Latency Waveform

The following table gives the output switching latency for different configurations in case of LUT_BANK_SWITCH_MODE = 0.

Table 2. Output Switch Latency
NUM_PHASES NUM_NLFs Output Switch Latency

(LUT bank switch mode = 0)
1 1 17
2 1 11
3 2 17
4 2 11
1 2 18
2 2 12

In case of LUT_BANK_SWITCH_MODE = 1, the switching is based on the LUT_BANK_SWITCH register. The LUT_BANK_SWITCH register writing latency increases the output switching latency.