LUT Access through the AXI4-Lite Interface - LUT Access through the AXI4-Lite Interface - 1.1 English - PG401

LUTs can be accessed on the AXI4-Lite interface using the LUT_TARGET and LUT_DATA registers. NLF1 LUT Target and NLF1 LUT Data registers access LUTs of the first NLF. If the design has two NLF blocks, the NLF2 LUT Target and NLF2 LUT Data registers access the second NLF LUTs. The format of these registers and procedure to access LUTs is identical for both NLF blocks.

The target location is one of the 256 (0 to 255) addresses of the selected LUT. There are two LUTs (LUT0, LUT1) for each NL unit and one NLF block has 16 (0 to 15) NL units. LUT Target register defines the target location by defining the target unit, target LUT and address within the target LUT.

LUT_ADDR (8-bit)

Use this 8-bit address to select one of the 256 (0 to 255) locations of LUT RAM.

LUT_ID (1-bit)

Each NLF dedicated block has two LUTs (LUT0/LUT1). This bit indicates the target LUT between LUT0 and LUT1.

UNIT_ID (4-bit)

Use this 4-bit address to select the target NL unit from the 16 available units.

The LUT Data register stores the LUT data. This data is written into or read from the target location. The target location is defined by the LUT Target register. LUT data is 32-bit complex with real data on the 16 LSBs and imaginary data on the 16 MSBs.

For more information, refer to Memory Address Map.