The following table defines the interface signals.
| Port | I/O | Width (bit) | Description |
|---|---|---|---|
| s_axi_ctrl_aclk | I | 1 | Clock for control interface. Synchronous operations on the control interface occur on the rising edge of this clock signal. |
| s_axi_ctrl_aresetn | I | 1 | Active-Low synchronous reset for the control interface. Resets the control interface logic to idle state but does not reset the configuration registers. |
| s_axi_ctrl_awvalid | I | 1 | Active-High input to the core. When asserted, the core reads
the address on the s_axi_ctrl_awaddr port, if
s_axi_ctrl_awready is High. |
| s_axi_ctrl_awaddr | I | 32 | Address to write control data. Core reads address when both
s_axi_ctrl_awvalid and s_axi_ctrl_awready are asserted High on a rising edge of s_axi_ctrl_aclk. |
| s_axi_ctrl_awready | O | 1 | Active-High output of the core. Indicates that the core is
ready for a valid address on the s_axi_ctrl_awaddr
port. |
| s_axi_ctrl_wvalid | I | 1 | Active-High input to the core. When asserted, the core reads
the data on the s_axi_ctrl_wdata port, if s_axi_ctrl_wready is High. |
| s_axi_ctrl_wdata | I | 32 | Control data to write to memory. Core reads data when both
s_axi_ctrl_wvalid and s_axi_ctrl_wready are asserted High on a rising edge of s_axi_ctrl_aclk. |
| s_axi_ctrl_wready | O | 1 | Active-High output of the core Indicates that the core is ready
for valid data on the s_axi_ctrl_wdata
port. |
| s_axi_ctrl_bvalid | O | 1 | Active-High output of the core. Asserted when the core has
completed the current write transaction and the write response is available on
s_axi_ctrl_bresp. |
| s_axi_ctrl_bresp | O | 2 | Write transaction response to master (00 = OKAY, 1X = ERROR, 01
= NA). The master reads response when both s_axi_bvalid and s_axi_bready are
asserted High on a rising edge of s_axi_ctrl_aclk. |
| s_axi_ctrl_bready | I | 1 | Active-High output of the master. Indicates that the master is
ready to read data on the s_axi_ctrl_bresp
port. |
| s_axi_ctrl_arvalid | I | 1 | Active-High input to the core. When asserted, the core reads
the address on the s_axi_ctrl_araddr port, if
s_axi_ctrl_arready is High. |
| s_axi_ctrl_araddr | I | 32 | Address to read control data. Core reads address when both
s_axi_ctrl_arvalid and s_axi_ctrl_arready are asserted High on a rising edge of s_axi_ctrl_aclk. |
| s_axi_ctrl_arready | O | 1 | Active-High output of the core. Indicates that the core is
ready for a valid address on the s_axi_ctrl_araddr
port. |
| s_axi_ctrl_rvalid | O | 1 | Active-High output of the core. Indicates that a valid data is
present on the s_axi_ctrl_rdata port. |
| s_axi_ctrl_rdata | O | 32 | Control data output of the core. Reads from a memory location
of the core. Master accepts data when both s_axi_ctrl_rvalid and s_axi_ctrl_rready are asserted High on a rising edge of s_axi_ctrl_aclk. |
| s_axi_ctrl_rresp | O | 2 | Read transaction response to the master (00 = OKAY, 1X = ERROR,
01 = NA). Master reads data when both s_axi_ctrl_rvalid and s_axi_ctrl_rready are asserted High on a rising edge of s_axi_ctrl_aclk. |
| s_axi_ctrl_rready | I | 1 | Active-High output of the master. Indicates that the master is
ready to read data on the s_axi_ctrl_rdata
port. |
| aclk | I | 1 | Clock for data interface and core operations. Synchronous operations on the data interface occur on the rising edge of this clock signal. |
| aresetn | I | 1 | Active-Low synchronous reset for the data interface and core
operations. Resets all the internal registers on aclk domain but it does not reset registers in s_axi_ctrl_aclk domain. |
| s_axis_din_tvalid | I | 1 | Active-High input to the core. When asserted, the core reads
the data on the s_axis_din_tdata port, if s_axis_din_tready is High. |
| s_axis_din_tready | O | 1 | Active-High output of the core. Indicates that the core is
ready for a valid data on the s_axis_din_tdata
port. |
| s_axis_din_tdata | I | C_AXIS_DIN_TDATA_WIDTH | Data input to the core. Core reads the data when both s_axis_din_tvalid and s_axis_din_tready are asserted High on a rising edge of aclk. Port width is specified at configuration based on
the number of samples per clock (NUM_PHASES)
C_AXIS_DIN_TDATA_WIDTH = NUM_PHASES*32. For more information,
refer to s_axis_din_tdata. |
| s_axis_din_tuser | I | C_AXIS_DIN_TUSER_WIDTH | It provides the index in case of external indexing. Core reads
the index when both s_axis_din_tvalid and s_axis_din_tready are asserted High on a rising edge of
aclk. Port width is specified at configuration,
based on NUM_PHASES. C_AXIS_DIN_TUSER_WIDTH =
NUM_PHASES*10. For more information, refer to s_axis_din_tuser. |
| m_axis_dout_tvalid | O | 1 | Active-High output of the core. Indicates that a. valid data
is present on m_axis_dout_tdata port. |
| m_axis_dout_tdata | O | C_AXIS_DOUT_TDATA_WIDTH | Data output from the core. Valid data is presents when m_axis_dout_tvalid is High. Port width is specified at
configuration based on NUM_PHASES.
C_AXIS_DOUT_TDATA_WIDTH = NUM_PHASES*56. For more information,
refer to m_axis_dout_tdata. |
| m_axis_dout_tuser | O | C_AXIS_DOUT_TUSER_WIDTH | I and Q output overflow status is given on this port. Port width is specified at configuration based on NUM_PHASES. C_AXIS_DOUT_TUSER_WIDTH = NUM_PHASES*4. For more information, refer to m_axis_dout_tuser. |
| s_axis_lut_config_tvalid | I | 1 | Active-High input to the core. When asserted, the core reads
the data on the s_axis_lut_config_tdata port, if
s_axis_lut_config_tready is High. This port is
available only when LUT access on AXI4-Stream is
enabled. |
| s_axis_lut_config_tready | O | 1 | Active-High output of the core. Indicates that the core is
ready for valid data on the s_axis_lut_config_tdata port. This port is available only when LUT
access on AXI4-Stream is enabled. |
| s_axis_lut_config_tdata | I | 56 | LUT data input to the core. Core reads LUT data when both
s_axis_lut_config_tvalid and s_axis_lut_config_tready are asserted High on a rising
edge of aclk. This port is available only when LUT
access on AXI4-Stream is enabled. For more
information, refer to s_axis_lut_config_tdata. |
| s_axis_lut_config_tuser | I | 8 | Bit-0 switches the LUT programming/readback between the two
NLFs.
This port is available only when LUT access on AXI4-Stream is enabled. |
| m_axis_lut_tvalid | O | 1 | Active-High output of the core. Indicates that a valid data
present on m_axis_lut_tdata port. |
| m_axis_lut_tdata | O | 32 | LUT data output from the core. Valid data is present when
m_axis_lut_tvalid is High. |
| enable | I | 1 | Active-High input to the core. Enables the core operations. The use-case for deassertion of the enable is for power savings when the block is not in use. For example, in time division duplexing (TDD). |
| lut_bank_select | I | 1 | Switches between PING PONG memories for LUT data. This is active only when LUT_BANK_SWITCH_MODE = 0 or fabric control (which is bit1 of LUT_BANK_SWITCH register) and also PP_LUT_MODE = 0 or direct fabric control. |
| m_axis_signal_dl_tvalid | O | 1 | Active-High output of the core. Indicates that a valid data
is present on m_axis_signal_dl_tdata port. |
| m_axis_signal_dl_tdata | O | C_AXIS_SIGNAL_DL_WIDTH | Tapped signal delay line output from the core. It is enabled by DL_OUT_EN register and the tap can be selected using SIGNAL_TAP_SELECT register. The width is specified at configuration based on NUM_PHASES. C_AXIS_SIGNAL_DL_WIDTH = NUM_PHASES*32 |
| m_axis_index_dl_tvalid | O | 1 | Active-High output of the core. Indicates that a valid data is
present on m_axis_index_dl_tdata port. |
| m_axis_index_dl_tdata | O | C_AXIS_INDEX_DL_WIDTH | Tapped index delay line output from the core. It is enabled by DL_OUT_EN register and the tap can be selected using INDEX_TAP_SELECT register. The width is specified at configuration based on NUM_PHASES. C_AXIS_INDEX_DL_WIDTH = NUM_PHASES*10 |
| status | O | 4 | Represents CORDIC overflow status, one bit for each phase. This is active only for internal indexing. |