Input/Output tdata (s_axis_din_tdata/m_axis_dout_tdata) - Input/Output tdata (s_axis_din_tdata/m_axis_dout_tdata) - 1.1 English - PG401

RFSoC DFE Non-Linear Filter LogiCORE IP Product Guide (PG401)
Document_ID
PG401
Release_Date
2026-06-23
Version
1.1 English

The slave interface (s_axis_din) receives the input TX (baseband) data. The master interface (m_axis_dout) transmits the output pre-distorted data. The number of phases determines the size of the tdata stream widths.

The basic element of the input data is a 32-bit complex sample. The sample contains 16-bit of real and imaginary signed data. It concatenates the real component in the lower 16-bit of the 32-bit word. The output is a 50-bit complex sample. It consists of 25-bit signed real and imaginary data, with the real component in the lower 25-bit of the 50-bit word.

The number of phases determines the total width of the input/output. Based on number of phases, the input data format is as shown in the following tables. To comply with the AXI4-Stream standards, scale the output width to 56*NUM_PHASES. Only the LSB 50*NUM_PHASES are occupied. The system does not drive valid data to the rest of the output width.

Table 1. s_axis_din_tdata Format
PH3 PH2 PH1 PH0
Q I Q I Q I Q I
127-112 111-96 95-80 79-64 63-48 47-32 31-16 15-0
Table 2. m_axis_dout_tdata_format (NUM_PHASES = 1)
  PH 0
Unused Q I
55-50 49-25 24-0
Table 3. m_axis_dout_tdata_format (NUM_PHASES = 2)
  PH 1 PH 0
Unused Q I Q I
111-100 99-75 74-50 49-25 24-0
Table 4. m_axis_dout_tdata_format (NUM_PHASES = 4)
  PH 3 PH 2 PH 1 PH 0
Unused Q I Q I Q I Q I
223-200 199-175 174-150 149-125 124-100 99-75 74-50 49-25 24-0

The following figures show the timing of the datapath for one-phase and four-phase designs.

Figure 1. One-Phase Datapath Timing Diagram

Figure 2. Four-Phase Datapath Timing Diagram