|
Core Specifics |
| Supported Device Family
1
|
AMD Zynq™
UltraScale+™ RFSoC
DFE |
| Supported User Interfaces |
AXI4-Stream, AXI4-Lite
|
| Resources |
Resource Use
|
| Provided with Core |
| Design Files |
Encrypted RTL |
| Example Design |
Reference Design Files |
| Test Bench |
Delivered in Co-Simulation package |
| Constraints File |
Xilinx Constraints File |
| Simulation Model |
Bit-accurate
MATLAB®
Model |
| Supported S/W Driver |
Not Provided |
| Tested Design Flows
2
|
| Design Entry |
Vivado Design Suite
|
| Simulation |
For supported simulators, refer to the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices,
refer to the AMD Vivado™
IP catalog.
- For the supported versions of third-party
tools, refer to the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|