- Supports two's complement 16-bit I and Q input samples and gives two's complement 25-bit I and Q output samples
- NLF based on look-up table (LUT) with 256-depth LUTs (8-bit indexing)
- Can be clocked up to 491.52 MHz on -2I and -2LVI speed grades on the RFSoC DFE device family
- Configurable samples per clock of 1, 2, 3, and 4 to support higher sampling rates of up to 1.96608 GSPS
- Programmable delay line taps for input signal and LUT indexing for each NL unit
- User-selectable LUT indexing mode
- User-selectable 32 and 64 non-linear terms
- Configurable LUT programming interface, either AXI4-Lite or AXI4-Stream
- Supports read-back of LUT content on either AXI4-Lite or AXI4-Stream
- Ping/pong LUT RAMs enable uninterrupted loading of LUT values
- Programmable output scaling to select the desired dynamic signal range at the output
- Supports tapping of signal and index from internal delay line circuits
- Supports low power mode of operation when not in use