Required Constraints
This section describes the constraints within the IP core XDC file. The AMD Vivado™ tool flow takes care of propagating all the IP core's synthesis constraints. The assumption is that external user inputs include only clock specifications. All other constraints are within the IP package.
In the design, there are two clock domains, aclk and s_axi_ctrl_aclk. The system treats
these clocks as asynchronous to each other. It does not time the paths between these
domains. The design takes care of these clock domain crossing paths for appropriate
deterministic behavior. <component_name>_clocks_xdc.xdc file included in the package takes care
of these timing exceptions.
Device, Package, and Speed Grade Selections
The RFSoC DFE Non-Linear Filter core runs on AMD Zynq™ UltraScale+™ RFSoC DFE devices.
Clock Frequencies
Refer to Resource Use for the recommended maximum clock frequencies.
Clock Management
Refer to Clocking for more details on clock management.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.