Configuration Tab - Configuration Tab - 1.1 English - PG401

The following figure shows the core configuration tab.

Figure 1. Configuration Tab

Component Name

Used as the base name of the output files generated for the core. The Vivado IP integrator takes the component name directly from the block diagram, making it unavailable in the customization GUI.

Allowed values: Names must begin with a letter and must be composed from the following characters: a through z, 0 through 9 and “_” (underscore).

Number of Phases (NUM_PHASES)

The RFSoC DFE Non-Linear Filter core can accept one, two, three, or four complex samples per clock cycle. The two, three, and four phase cases allows the core to support two, three, and four times higher sampling rates with increased area usage. Depending on the selected configuration, the width of buses (s_axis_din, m_axis_dout, m_axis_signal_dl, and m_axis_index_dl) scales appropriately.

Note: For the one-phase design, select 1 from the list menu.

Numbers of Non-Linear Filters (NUM_NLFs)

Number of NLF blocks enabled to complete the computation at required rate. The core can support 32 non-linear terms with one NLF when configured for one or two samples per clock. When you configure for three or four samples per clock, you need two NLFs to support 32 non-linear terms. Each NLF block requires two phases. Two NLF blocks are required to support 64 non-linear terms for one or two samples per clock cycle.

Note: The current version of the IP cannot support 64 non-linear terms for three or four samples per clock cycle.

LUT RAM Access on AXI4-Stream (LUT_AXIS_EN)

User selection to enable LUT RAM access on s_axis_lut_config interface. The write and read back operations are performed through the s_axis_lut_config and m_axis_lut interfaces. Refer to Figure 1 for the I/O changes when LUT Access via AXI4-Stream is set to 1.

Figure 2. LUT Access via AXI4-Stream Set to 0