Clocking - Clocking - 1.1 English - PG401

This core requires the following clock input signals.

aclk

Drives the main data interface logic within the design. The clock frequency determines the data rate of the RFSoC DFE Non-Linear Filter IP core. All AXI4-Lite interfaces (s_axis_din, m_axis_dout, s_axis_lut_config, m_axis_lut, m_axis_signal_dl, and m_axis_index_dl) are synchronous to this clock.

s_axi_ctrl_aclk

Used to time all transfers on the s_axi_ctrl interface.