The DPUCADF8H top-level interfaces are shown in the following figure.
Figure 1. DPUCADF8H Ports
The DPUCADF8H I/O signals are listed and described in the following table.
| Signal Name | Interface Type | Width | I/O | Description |
|---|---|---|---|---|
| s_axi_control | Memory mapped AXI slave interface | 32 | I/O | 32-bit memory mapped AXI interface for registers. |
| ap_clk | Clock | 1 | I | Input clock used for AXI logic. |
| ap_clk_2 | Clock | 1 | I | Input clock used for DPU general logic. |
| ap_rst_n | Reset | 1 | I | Active-Low reset for AXI logic. |
| ap_rst_n_2 | Reset | 1 | I | Active-Low reset for DPU general logic. |
| m00_axi | Memory mapped AXI master interface | 512 | I/O | 512-bit memory mapped AXI interface for DPU. |
| interrupt | Interrupt | 1 | O | Active-High interrupt output from DPU. |