The DPU generates an interrupt to signal the completion of a task. A high
state on ap_start signals the start of a DPU task. At the
end of the task, the DPU generates an interrupt and bit0 in AP_ISR is set to 1.
To support DPU interrupt, the Interrupt Controller module implements the following registers:
- AP Global Interrupt Enable Register (AP_GIER)
- Provides the master enable/disable for the interrupt output to the processor or Interrupt Controller. See AP Global Interrupt Enable Register (AP_GIER) in Table 1 for more details.
- AP Interrupt Enable Register (AP_IER)
- Implements the independent interrupt enable bit for each channel. See AP Interrupt Enable Register (AP_IER) in Table 1 for more details.
- AP Interrupt Status Register (AP_ISR)
- Implements the independent interrupt status bit for each channel. The AP_ISR provides Read and Toggle-On-Write access. The Toggle-On-Write mechanism allows interrupt service routines to clear one or more ISR bits using a single write transaction. The AP_ISR can also be manually set to generate an interrupt for testing purposes. See AP Interrupt Status Register (AP_ISR) in Table 1 for more details.