Clocking - 1.0 English

There are two clock domains in the DPUCADF8H IP: the ap_clk and ap_clk2. There are two reset signals associated with the two clocks: the ap_rst_n and ap_rst_n_2.

ap_clk

The ap_clk is associated with all AXI4 interfaces, both m00_axi and s_axi_control. The data transfer between the DPUCADF8H and external memory happens in the ap_clk clock domain.

ap_clk2

The DPUCADF8H core works with the ap_clk2 and its derivative clock.