The following clocks are used in the AMD Versal™ Adaptive SoC GT Controller for DisplayPort and SDI:
| Clock | I/O | Description |
|---|---|---|
| gt_ctrl_aclk | I | Free running clock that is used to bring up the Versal device GT and to clock GT helper blocks. Note: For rate switching logic and GT to function
properly, this value must be 100 MHz.
|
| gt_txusrclk | I | TXUSRCLK2 of master transceiver channel. |
| gt_rxusrclk | I | RXUSRCLK2 of master transceiver channel. |
| clk_100mhz | I | 100 MHz clock used for UHD-SDI operations. Note: For rate switching logic and GT to function
properly, this value must be 100 MHz.
|
For more information on clocking, see Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).