Register Address Space for Warp Filter - 1.1 English

Video Warp Processor LogiCORE IP Product Guide (PG396)
Document ID
PG396
Release Date
2024-07-01
Version
1.1 English
Table 1. Register Address Space for Warp Filter
Address (hex) BASEADDR+ Register Name Access Type Register Description
0x0000 Control Signals R/W Bit[0] = ap_start(R/W/COH) 2
Bit[1] = ap_done(R/COR) 3
Bit[2] = ap_idle(R)
Bit[3] = ap_ready(R)
Bit[7] = auto_restart(R/W)
Others = Reserved
0x00004 Global Interrupt Enable R/W Bit[0] = Global interrupt enable
Others = Reserved
0x00008 IP Interrupt Enable R/W Bit[0] = ap_done
Bit[1] = ap_ready
Others = reserved
0x0000C IP Interrupt Status register R/TOW 1 Bit[0] = ap_done
Bit[1] = ap_ready
Others = Reserved
0x00010 Descriptor Address register 0 R/W Bit[31] to Bit[0] = LSB 32 bits of the descriptor address
0x00014 Descriptor Address register 1 R/W Bit[31] to Bit[0] = MSB 32 bits of the descriptor address
  1. TOW – toggle on write.
  2. COH – clear on handshake.
  3. COR – clear on read.
  4. The Control register (0x0000), Global Interrupt Enable register (0x0004), IP Interrupt Enable register (0x0008), and IP Interrupt Status register (0x000C) are explained in section S_AXILITE Control Register Map of UG1399. In UG1399, these register definitions might have some additional bits, but in this IP, only bits mentioned in this table are accessed. Consider only these bits when accessing the Control register, Global Interrupt Enable register, IP Interrupt Enable register, and IP Interrupt Status register.

Register Description

Control (0x00000) register
This register controls the operation of the Filter. Bit[0] of the Control register, ap_start, kicks off the core from software. Writing 1 to this bit starts the core to generate a video frame. To set the core in free running mode, Bit[1] of the Control register, ap_done, indicates when the IP has completed all operations in the current transaction. A logic 1 on this signal indicates that the IP has completed all operations in this transaction.

Bit[2] of the Control register, ap_idle, signal indicates if the IP is operating or idle (no operation). The idle state is indicated by logic 1. This signal is asserted Low when the IP starts operating. This signal is asserted High when the IP completes operation and no further operations are performed.

Bit[3] of the Control register, ap_ready, signal indicates when the IP is ready for new inputs. It is set to logic 1 when the IP is ready to accept new inputs, indicating that all input reads for this transaction are completed. If the IP has no operations in the pipeline, new reads are not performed until the next transaction starts. This signal is used to make a decision on when to apply new values to the input ports and whether to start a new transaction. Bit[3] to Bit[6] are not used.

Bit[7] of the Control register, auto_restart, can be set to enable the auto-restart mode and then the IP restarts automatically at the end of each transaction.

Global Interrupt Enable (0x00004) register
This register is the master control for all interrupts. Bit[0] can be used to enable or disable all core interrupts.
IP Interrupt Enable (0x00008) register
This register allows interrupts to be enabled selectively. Currently, two interrupt sources are available: ap_done and ap_ready. ap_done is triggered after the frame processing is complete, and ap_ready is triggered after the core is ready to start processing the next frame.
IP Interrupt Status (0x0000C) register
This is a dual-purpose register. When an interrupt occurs, the corresponding interrupt source bit is set in this register. In readback mode (get status), the interrupting source can be determined. In writeback mode (clear interrupt), the requested interrupt source bit is cleared.
IP Descriptor Address Register 0 (0x00010) register
This register allows to configure the LSB 32-bit of the 64-bit descriptor address to the IP.
IP Descriptor Address Register 0 (0x00014) register
This register allows to configure the MSB 32-bit of the 64-bit descriptor address to the IP.