The Warp Initializer and Warp Filter have specific registers that allow you to control the operation of the core. All registers have an initial value of 0.
The following table provides a detailed description of all the registers that apply globally to the IP.
| Address (hex) BASEADDR+ | Register Name | Access Type | Register Description |
|---|---|---|---|
| 0x0000 | Control Signals | R/W | Bit[0] = ap_start (R/W/COH) 2 |
| Bit[1] = ap_done (R/COR) 3 | |||
| Bit[2] = ap_idle (R) | |||
| Bit[3] = ap_ready (R) | |||
| Bit[7] = auto_restart (R/W) | |||
| Others = Reserved | |||
| 0x00004 | Global Interrupt Enable | R/W | Bit[0] = Global interrupt enable |
| Others = Reserved | |||
| 0x00008 | IP Interrupt Enable | R/W | Bit[0] = ap_done |
| Bit[1] = ap_ready | |||
| Others = reserved | |||
| 0x0000C | IP Interrupt Status register | R/TOW 1 | Bit[0] = ap_done |
| Bit[1] = ap_ready | |||
| Others = Reserved | |||
| 0x00010 | Descriptor Address register 0 | R/W | Bit[31] to Bit[0] = LSB 32 bits of the descriptor address |
| 0x00014 | Descriptor Address register 1 | R/W | Bit[31] to Bit[0] = MSB 32 bits of the descriptor address |
| 0x00020 | MAXI Control Address register | R/W | Bit[31] to Bit[0] = Program 0 into this register. |
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Register Description
- Control (0x00000) register
- This register controls the operation of the Warp Initializer. Bit[0]
of the Control register,
ap_start, kicks off the core from software. Writing 1 to this bit starts the core.Bit[1] of the Control register,
ap_done, indicates when the IP has completed all operations in the current transaction. A logic 1 on this signal indicates that the IP has completed all operations in this transaction.Bit[2] of the Control register,
ap_idle, indicates if the IP is operating or idle (no operation). The idle state is indicated by logic 1. This signal is asserted Low when the IP starts operating. This signal is asserted High when the IP completes operation and no further operations are performed.Bit[3] of the Control register,
ap_ready, indicates when the IP is ready for new inputs. It is set to logic 1 when the IP is ready to accept new inputs, indicating that all input reads for this transaction are completed. If the IP has no operations in the pipeline, new reads are not performed until the next transaction starts. This signal is used to make a decision on when to apply new values to the input ports and whether to start a new transaction. Bit[3] to Bit[6] are not used.Bit[7] of the Control register,
auto_restart, can be set to enable the auto-restart mode and then the IP restarts automatically at the end of each transaction. - Global Interrupt Enable (0x00004) register
- This register is the master control for all interrupts. Bit[0] can be used to enable or disable all core interrupts.
- IP Interrupt Enable (0x00008) register
- This register allows interrupts to be enabled selectively. Currently,
the following interrupt sources are available:
ap_doneandap_ready.ap_doneis triggered after the frame processing is complete, andap_readyis triggered after the core is ready to start processing the next frame. - IP Interrupt Status (0x0000C) register
- This is a dual purpose register. When an interrupt occurs, the corresponding interrupt source bit is set in this register. In the readback mode (get status), the interrupting source can be determined. In the writeback mode (clear interrupt), the requested interrupt source bit is cleared.
- IP Descriptor Address Register 0 (0x00010) Register
- This register allows to configure the LSB 32-bit of the 64-bit descriptor address to the IP.
- IP Descriptor Address Register 0 (0x00014) Register
- This register allows to configure the MSB 32-bit of the 64-bit descriptor address to the IP.
- IP MAXI Control Address (0x00020) Register
- This register is the Warp Initializer Control address. Program 0 into this register.