Application Software Development - 1.1 English

Video Warp Processor LogiCORE IP Product Guide (PG396)
Document ID
PG396
Release Date
2024-07-01
Version
1.1 English

The Warp Initializer and Warp Filter cores are delivered with bare-metal drivers as part of the AMD Vitis™ software platform installation. The driver follows a layered architecture, where layer 1 provides basic register peek/poke capabilities and requires you to be familiar with the register map and inner workings of the core. Layer 2 abstracts away all the lower level details and provides an easy to use functional interface to the IP. AMD recommends using layer 2 APIs to interact with the core.

Building the BSP

While building the board support package (BSP), the driver extracts the Warp Initializer and Warp Filter IP hardware configuration settings from the provided hardware design file.

Modes of Operation

Both IPs support the interrupt mode of operation. In interrupt mode, the interrupt (IRQ) port of the core needs to be connected to a system interrupt controller. When an interrupt is triggered, the core interrupt service routine (ISR) checks to confirm if the current frame processing is complete. It then calls a user programmable callback function, if any. In the callback function, the register settings for the next frame should be programmed, that is, which source memory buffer address a frame should read from next. Finally, the interrupt service routine triggers the core to start processing the next frame. An application must perform the following tasks to configure the core for the interrupt mode:

  • Register the Warp Initializer core ISR routine XVWarpInit_IntrHandler and Warp Filter core ISR routine XVWarpFilter_IntrHandler with the system interrupt controller.
  • Register the application callback function that should be called within the interrupt context. This can be done using the API XWarpInit_callback for the Warp Initializer interrupt, and XWarpFilter_callback for the Warp Filter IP.
  • Enable the interrupts for both IPs by calling API XVWarpInit_EnableInterrupts and XVWarpFilter_InterruptEnable respectively.

Usage

Use the following steps to integrate and use the driver in the application:

Figure 1. Flowchart for Operation

  1. Include the driver header files xv_warp_init_gen_l2.h and xv_warp_filter_l2.h.
  2. Declare an instance of the Warp Initializer type XV_warp_init WarpInitInst, and an instance of the Filter type XV_warp_filter WarpInst.
  3. Initialize the Warp Initializer and Warp Filter instance at power on:
    int XV_warp_ Initialize (XV_warp_init *InstancePtr, u16 DeviceId);
    int XV_warp_filter_Initialize (XV_warp_filter *InstancePtr, u16 DeviceId);

    This function accesses the hardware configuration and initializes the core instance structure.

  4. The application must register the ISRs for both the cores with the system interrupt controller and set the application callback function. This function is called by the driver when the frame done IRQ is triggered.
  5. Enable the Warp Initializer IP interrupt:
    void XVWarpInit_EnableInterrupts(XV_warp_init *InstancePtr, u32 Mask);
  6. Fill the Warp Initializer descriptor and start the IP:
    int XVWarpInit_ProgramDescriptor(XV_warp_init *InstancePtr, u32 Descnum, XV_warp_init_InputConfigs *ConfigPtr);
    int XVWarpInit_start_with_desc(XV_warp_init *InstancePtr, u32 descnum);
  7. Wait for the interrupt.
  8. Enable the Warp Filter IP interrupt:
    void XVWarpFilter_InterruptEnable(XV_warp_filter *InstancePtr, u32 Mask);
  9. Fill the Warp Filter descriptor and start the IP:
    void XVWarpFilter_ProgramDescriptor(XV_warp_filter *InstancePtr, u32 DescNum, XV_warp_filter_InputConfigs *configPtr, U32 valid_seg, U32 lblock_count, U32 line_num);
    void XVWarpFilter_Start(XV_warp_filter *InstancePtr);
  10. Wait for the interrupt and update the buffer addresses of the next frame.