Supported PRACH Formats - Supported PRACH Formats - 2.0 English

Supported PRACH Formats - Supported PRACH Formats - 2.0 English - PG391

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID

PG391

Release Date

2025-11-26

Version

2.0 English

The following table lists the PRACH formats supported by the core.

Table 1. Supported PRACH Formats
RAT Type	PRACH Parameters					PRACH Output		CC Baseband Rate
	Format	SCS (kHz)	BW (MHz)	Seq Len	RB BW (MHz)	Rate (MSPS)	FFT Size	15.36¹	30.72	61.44	122.88	245.76
	Format	SCS (kHz)	BW (MHz)	Seq Len	RB BW (MHz)	Rate (MSPS)	FFT Size	Decimation Ratio
LTE	0,1,2,3	1.25	1.05	839	1.08	1.28	1024	12	24
LTE	4	7.5	1.05	139	1.08	1.92	256	8	16
FR1 NR 15 kHz SCS	0,1,2	1.25	1.05	839	1.08	1.28	1024	12	24	48
	3	5	4.2	839	4.32	5.12	1024	3	6	12
	A1,A2, A3,B1, B2,B3, B4 C0,C2	15	2.1	139	2.16	3.84	256	4	8	16
		15	17.26	1151	17.28	30.72	2048			2
		30	4.2	139	4.32	7.68	256	2	4	8
		30	17.16	571	17.28	30.72	1024			2
FR1 NR 30 kHz & 60 kHz SCS	0,1,2	1.25	1.05	839	1.08	1.28	1024	12	24	48	96
	3	5	4.2	839	4.32	5.12	1024	3	6	12	24
	A1,A2, A3,B1, B2,B3, B4 C0,C2	15	2.1	139	2.16	3.84	256	4	8	16	32
		15	17.26	1151	17.28	30.72	2048			2	4
		30	4.2	139	4.32	7.68	256	2	4	8	16
		30	17.16	571	17.28	30.72	1024			2	4
FR2 NR 60 kHz & 120 kHz SCS	A1,A2, A3,B1, B2,B3, B4 C0,C2	15	17.26	1151	17.28	30.72	2048			2	4	8
		30	17.16	571	17.28	30.72	1024			2	4	8
		60	8.4	139	8.64	15.36	256			4	8	16
		120	16.8	139	17.28	30.72	256			2	4	8
NB IOT	0,1	3.75	0.18	48	0.18	0.96	256	16
NB IOT	0,1	3.75	0.18	48	0.18	1.92	512		16
Only supported for 122.88 MHz and 245.76 MHz clock rates.

Note: The table shows the supported PRACH formats for a single PRACH modulation frequency. It is possible to transmit one, two, four, or eight PRACH channels adjacent in frequency. The core allows these to be extracted using a single configuration.

You can extract more than one PRACH channel by reducing the decimation rate. Lower the rate by a factor equivalent to the number of channels. Increase the FFT size by the same factor. When extracting multiple channels in this manner, select the demodulation frequency to ensure that it is in the center of all of the extracted channels.

Configuring for extraction of multiple channels adjacent in frequency increases the bandwidth of the output signal.

The core has a memory mapped AXI4-Lite interface for configuration, status readback and control, including static PRACH channel scheduling. An optional IRQ output is also available to enable a processor to interrupt on error conditions. An optional AXI4-Stream control interface is also available to support real-time dynamic PRACH channel scheduling.

A software driver is included. It provides all the API functions required to set up and operate the DFE PRACH core, such as NCO and DDC configuration. The API can instruct changes to the carrier interleaving sequence, enabling/disabling of carriers and antennas, and entry into and exit from low power mode. You can schedule these configuration updates to take place according to a chosen trigger event.

Triggering of control changes can be either immediate or based on arbitrary transitions on selected bits of the TUSER input bus.