Resets - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID
PG391
Release Date
2024-05-30
Version
2.0 English

The DFE PRACH core has two resets, s_axis_aresetn and s_axi_aresetn, corresponding to the two clock domains described above. These signals are active-Low.

s_axis_aresetn resets the core to its default state. To achieve this, assert the reset signal for at least sixty active clock cycles. After a reset, the core enters its lowest power state in which the datapath is disabled, no component carriers are configured and no PRACH captures are scheduled. All events are cleared and all interrupts are disabled. The data pipeline within the DDC filter chain is cleared to 0.

The s_axi_aresetn is part of the AXI4-Lite bus infrastructure and allows the memory mapped AXI4-Lite interface logic to be reset along with other peripherals connected to the bus.

The core is ready for operation on the first clock cycle following the deassertion of s_axis_aresetn or s_axi_aresetn, whichever comes later.

It is strongly recommended that both reset signals remain asserted at system startup until both s_axis_aclk and s_axi_aclk are stable. Attempting to operate the AXI4-Lite interface without the s_axis_aclk present, or to operate the PRACH datapath without the s_axi_aclk present, may lead to unexpected behavior and system instability.