Port Descriptions - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID
PG391
Release Date
2024-05-30
Version
2.0 English

The core interfaces are shown in the following figure.

Figure 1. Core Ports

The widths of the data buses within the DIN0, DIN1, DIN2, and DOUT AXI4-Stream interfaces are determined by the sample width, the number of antennas in each band, and the antenna interleaving factor for that band chosen when the core is customized.

For each band, the data input interface carries multiplexed data for multiple component carriers and antennas. The width is NL×IW×2, where NL is the number of antenna lanes allocated for a given band and IW is the input sample width (16 for 16-bit samples and 24 for 18-bit samples).

NL is calculated as the number of antennas in a band divided by the antenna interleaving factor for that band. For example, with eight antennas and an antenna interleave factor of 2, the number of antenna lanes NL equals 4.

The number of antennas and the antenna interleaving factor can be specified independently for each band. However, the total number of antenna lanes across all active bands cannot exceed 6 and if any active band uses a single antenna, no other active band can use eight antennas.

The data output interface carries multiplexed data for multiple RACH channels and antennas. The width is NRL×16×2, where NRL is the number of PRACH lanes. The number of PRACH lanes, 1 or 2, is specified at core configuration, with the restriction that if any band uses eight antennas, the number of PRACH lanes must be 2 and if any band uses single antenna, the number of PRACH lanes must be 1. If two or four antennas are used, for each of the active bands, then the number of PRACH lanes can be selected to be either 1 or 2, according to requirements. Selecting 2 will give a greater output bandwidth from the DFE PRACH core, but may require additional resources.

The TUSER buses associated with the data input interfaces have a width of UW bits. This can be specified on a per band basis when the core is configured. The TUSER bus associated with the output of the core is supplied on an AXI4-Stream interface which is separate from the Data out interface. This interface will output the TUSER inputs for each band, adjusted for latency and concatenated to form a single wide bus.