PRACH Extraction using Internal Scheduler - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID
PG391
Release Date
2024-05-30
Version
2.0 English

A PRACH transmission by a UE consists of a cyclic prefix (CP), followed by one or more repetitions of a RACH sequence, followed by a guard period. The entire transmission, including the CP and guard period, can be repeated immediately following the original transmission.

RACH transmissions can only occur at certain permitted times, so extraction events must therefore be scheduled with respect to the radio frame structure.

If the "Remove Internal Scheduling" option is left unchecked at core generation, the DFE PRACH core will include a scheduling controller which tracks the current system time in terms of the current frame number, and the time elapsed since the start of the last frame. The API allows this timer to be synchronized by triggering it to restart on a frame boundary marker, which can be supplied as a pulse on a user-defined bit of the TUSER bus. There is one trigger per band, allowing each band to have independent frame timing. Each band's timing reference is shared across all CCs and antennas for that band. The core examines each RACH channel's configuration to determine which timing reference applies and synchronizes that channel to the appropriate reference.

Different CCs may have different 5G numerologies. The scheduling controller uses the sub-carrier spacing for each CC to determine the position of sub-frames and slots within the radio frame for that CC. This allows the starting position and duration of RACH extraction events to be specified in frames, sub-frames and slots. The scheduling controller compares the current time against the scheduled capture events for all active RACH channels and ensures that new PRACH captures are triggered at the appropriate times.

Each RACH channel can receive scheduling information in one of the two ways: static scheduling through the API or dynamic scheduling through the optional AXI4-Stream control interface. These scheduling methods are described in the following sections.