Memory Mapped AXI4-Lite Interface Ports - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)
Document ID
PG391
Release Date
2024-11-20
Version
2.0 English
Port Name I/O Clock Description
s_axi_ctrl_arready O s_axi_aclk Indicates that the core is ready for a read address on s_axi_ctrl_araddr.
s_axi_ctrl_arvalid I s_axi_aclk Indicates that the bus logic is providing a read address on s_axi_ctrl_araddr.
s_axi_ctrl_araddr[17:0] I s_axi_aclk Read address. Accepted when s_axi_ctrl_arready and s_axi_ctrl_arvalid are High on the same clock cycle.
s_axi_ctrl_awready O s_axi_aclk Indicates that the core is ready for a write address on s_axi_ctrl_awaddr.
s_axi_ctrl_awvalid I s_axi_aclk Indicates that the bus logic is providing a write address on s_axi_ctrl_awaddr.
s_axi_ctrl_awaddr[17:0] I s_axi_aclk Write address. Accepted when s_axi_ctrl_awvalid and s_axi_ctrl_awready are asserted on the same clock cycle.
s_axi_ctrl_bready I s_axi_aclk Indicates that the bus logic is ready to receive a write transaction response.
s_axi_ctrl_bvalid O s_axi_aclk Indicates that the core has completed a write transaction and the response on s_axi_ctrl_bresp is valid.
s_axi_ctrl_bresp[1:0] O s_axi_aclk Write transaction response (00 = OK, 1x = ERROR).
s_axi_ctrl_rready I s_axi_aclk Indicates that the bus logic is ready to receive read data.
s_axi_ctrl_rvalid O s_axi_aclk Indicates that the core has completed a read transaction and that the data on s_axi_ctrl_rdata and response on s_axi_ctrl_rresp are valid.
s_axi_ctrl_rresp[1:0] O s_axi_aclk Read transaction response (00 = OK, 1x = ERROR).
s_axi_ctrl_rdata[31:0] O s_axi_aclk Read data.
s_axi_ctrl_wready O s_axi_aclk Indicates that the core is ready to receive write data on s_axi_ctrl_wdata.
s_axi_ctrl_wvalid I s_axi_aclk Indicates that the bus logic is providing write data on s_axi_ctrl_wdata.
s_axi_ctrl_wdata[31:0] I s_axi_aclk Write data.
irq O s_axi_aclk Interrupt request to processor. (Not part of the AXI4-Lite standard set of signals.)