Low Power Mode - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID
PG391
Release Date
2024-05-30
Version
2.0 English

For certain use cases such as time-division duplex (TDD) operation, the DFE PRACH core can be placed periodically into a low-power state. In this state the PRACH datapath functions are disabled and the data output from the core does not change. The control logic remains operational and the core continues to track the CCID sequence and radio frame location.

Entry into and exit from low power mode are expected to be timed using a continuous trigger that recurs automatically without any need for software intervention between events. The following code shows an example of how to set up a periodic low-power transition.

/* Declare and populate trigger configuration */
XDfePrach_TriggerCfg TriggerCfg;

TriggerCfg.LowPower.Mode = 2;            // Continuous trigger 
TriggerCfg.LowPower.TUSERBit = 7;        // on bit 7
TriggerCfg.LowPower.TuserEdgeLevel = 0;  // when Low  

/* Put the trigger into effect */
XDfePrach_SetTriggersCfg(InstancePtr, &TriggerCfg);

Following the call to XDfePrach_SetTriggersCfg, the core will enter the low power state whenever bit 7 of s_axis_din0_tuser is 0 and will return to normal operation whenever the bit returns to 1.

The low power state can only be applied using band 0 TUSER as a trigger. Low power applies across the whole core and will place all the RCIDs, and hence all captures across all bands in a low-power state. To disable RCIDs on a per band basis, the normal RCID enable mechanism in the API should be used.

Upon seeing the low power trigger, the core will enter the low power state after a two clock cycle delay. Any captures which overlap with the low power period will be forced to terminate; however, it can take up to 15.625 μs to effectively reach the low power state to terminate any running captures. Exiting the low power state will also occur after a two cycle latency. Any captures scheduled to begin after leaving low power will start at their programmed time.

To achieve the lowest possible power consumption from the core, it must be deactivated using the XDfePrach_Deactivate function. This places all the logic into a quiescent state and disables the clock to the underlying primitive. To reactivate the core, use the XDfePrach_Activate function following the procedure described in the Initialization section.

Note: Low power mode should be avoided when the core is configured for more than a single band.